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SDA 5248-5
Teletext Processor
Preliminary Data Features
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SDA 5248-5
MOS IC
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I2C bus interface with complete direct access to the memory area. Uses 64 Kx4 and 256 Kx4 dynamic RAM's Can store 32 or 128 teletext pages and acquire 4 pages simultaneously Optional assignment of the 4 acquisition circuits and bank select of the 128 memory areas via the 8 page memory pointers Suitable for TOP Text Access page display via page memory pointers
P-DIP-40-1
I2C bus interface with complete direct access to the memory area q Memory clear function for 8 pages after power-on
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Memory clear function via I2C bus for all pages Internal 24-MHz PLL for memory tuning 2 free programmable circuit outputs 12x10 dot matrix for characters and graphic Extra display row for status messages Acquisition during the vertical blanking interval or for cable text during all lines 60-Hz recognition and display without additional hardware Field detection for non-interlace display STATUS information for asynchronous operation Forced synchronization possibility to the CBVS signal either by inferior signal quality West European character set SDA 5248-5C1 East European character set SDA 5248-5C2 Turkish character set SDA 5248-5TR Ordering Code Q67100-H5074 Q67100-H5052 Q67100-H5127 Package P-DIP-40-1 P-DIP-40-1 P-DIP-40-1
Type SDA 5248-5C1 SDA 5248-5C2 SDA 5248-5TR
Semiconductor Group
23
08.93
SDA 5248-5
The SDA 5248-5 multipage text is a derivate of the SDA 5243 including some additional functional blocks. Using this device it is possible tp process up to 128 pages stored in an external DRAM. The relation between the 4 acquisition circuits available and the addresses of the page memory can be handled much more flexible than before. In the SDA 5248-5 chip there is now a version of our teletext processors available that can manage up to 128 pages of teletext in an external dynamic RAM. SDA 5248-5 is upward compatible in software with SDA 5243 and can be operated in the same hardware environment as the latter and with the same SDA 5231-2 data slicer. The pinning differs only where the memory interface is concerned. SDA 5248-5 offers extra features however:
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For memory it only requires a dynamic RAM in x4 organization: 64 K x 4 dynamic RAMs can be used for 32 teletext pages or 256 K x 4 for 128 pages. The control signals of the memory interface are all derived from the 24-MHz timing, which is generated by an internal PLL. The extra external circuitry necessary for this consists of an RC filter and the wiring of the analog power supply. There is no longer firm assignment of memory address and search circuit in SDA 5248-5. Each of the four search circuits, independently of one another, can be assigned one of 128 memory addresses. This makes management of the pages that have already been found very much more flexible. There is no waiting for the reception of four complete teletext pages an the reprogramming of the memory-bank selection, which is only then possible, and the selection of four new teletext pages, as is the case with SDA 5243. As soon as a complete teletext page has been received, a new memory area can be selected for the search circuit and a new teletext page programmed. In this way 128 pages can be read in more efficiently or part of the sent teletext pages stored faster. There are substantial advantages here, especially for use in TOP. Sufficient block, group and information pages can be found and loaded faster. So this does away with the long waiting times until the TV viewer sees the teletext pages. Two switching outputs, programmable on the I2C bus, can be used to control external functions.
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Semiconductor Group
24
SDA 5248-5
The Teletext Processor SDA 5248-5 contains six function blocks (see block diagram):
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Control with timing and system clock Data acquisition Memory interface with 24-MHz PLL Character generator I2C bus Refresh generator and synchronization
Teletext data and clock signals from the data slicer SDA 5231-2 are transferred to the TTX processor SDA 5248-5 via pins TTD and TTC. The required data are selected in the acquisition section and stored in the external RAM via the memory interface. The data read from the RAM passes through the memory interface to the character generator, where they are transformed into corresponding R, G, B signals for the video output stages. Further output signals produced include a blanking signal BLAN, a contrast reducing signal COR and a text signal Y for an external printer. 23 registers can be written and 1 register can be written and read over the I2C bus (diagram 5, 6 and 7).
Semiconductor Group
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SDA 5248-5
Block Diagram Teletext Processor with DRAM Interface
Semiconductor Group
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SDA 5248-5
Pin Configuration (top view)
Semiconductor Group
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SDA 5248-5
Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol V DD A7 A8 SO S1 TTD TTC EVEN F6 VCS Function +5 V RAM Address RAM Address Switching Signal Switching Signal Teletext Data Teletext Clock EVEN Field System Clock Composite Sync Operation with dynamic memories with 4bit organization When connection of 256 Kx4 Free programming switching signal Free programming switching signal From data slicer SDA 5231 6.9375 MHz from data slicer SDA 5231 Field recognition output 6-MHz from data slicer SDA 5231 Sliced sync signal, part of the CVBS signal, coming from the data slicer SDA 5231. Three-level signal for SDA 5231 for synchronization of F6. Synchronization output during text reproduction. Open drain video output signal for TV output stages. Open drain video output signal for contrast reduction. Blanking signal open drain output Open drain video output signal for black/ white I2C bus clock input Bidirectional I2C bus data port (open drain stage) Description
11 12 13, 14, 15 16 17 18 19 20 21 22 23
SAND
SANDCASTLE
TCS/SCS Sync Input/Output RGB COR BLAN Y SCL SDA V SS V SSA RC Red, Green, Blue Contrast Reduction Blanking Character Output Serial Clock Serial Data Ground Digital Ground Analog RC
Analog ground for PLL RC network for PLL loop to VSSA
Semiconductor Group
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SDA 5248-5
Pin Definitions and Functions (cont'd) Pin No. 24 25 26-29 30 31 32 33 34-40 Symbol V DDA N.C D0-D3
WE RAS CAS OE
Function + 5V N.C RAM Data Write Enable Row Address Strobe Column Address Strobe Output Enable RAM Address
Description Analog voltage supply for PPL Output always low Tristate bidirectional data port RAM control signal (active low) Control signal (active low) RAM control signal (active low) RAM control signal (active low) Operation with dynamic memories with 4bit organization.
A0-A6
Circuit Description Data Acquisition The SDA 5248-5 meets all the requirements of the present teletext standard. Data arriving at the TTD pin are accepted as teletext data as soon as the start code (diagram 1) appears within the data entry window. All bytes are checked for odd parity errors and 1-bit errors are corrected in the bytes with Hamming protection. The parity check for the data bytes can be deselected for reception of 8-bit data without parity. The following acquisition features are available:
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Automatic data font changeover to one of 6 language by transmitted control bits, independent of the selection over the I2C bus (diagram 8 and 10). Data reception during lines 2 through 22 in each half frame. Data reception in all lines of a full frame by switching over to full channel operation. In full channel operation one must note that the automatic erase function is only partially available, hence all lines of every page must be transmitted in sequence or the whole page erased by software. Memory control of storage of up to 128 teletext page, 4 teletext pages are sought simultaneously and when received are transferred into the memory bank selected by the page memory pointers (diagram 7, register 13). In the "don't care" mode pages can be sought whose page numbers are not precisely know, by inserting a don't care bit in place of the unknown number. This causes a search for all numbers between 0HEX and FHEX at the indicated location (diagram 5, register 3). Capability of receiving supplementary information (ghost rows) which can be processed in a microcomputer. This allows reception of 24 virtual lines per page in addition to the normal text lines, and 2 Kbytes of memory are needed to store one page (diagram 2b). 29
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Semiconductor Group
SDA 5248-5
SDA 5248-5
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The transmitted clock time is directly written into page memory selected for display. Automatic erasing of stored pages 0-7 for standard teletext. Erasure of single pages by software command. Rolling page number during search.
Character Generation The character generator provides 192 alphanumeric characters and 2x64 graphics symbols in a raster comprising 12 horizontal and 10 vertical points. The various display possibilities can be selected by means of 32 control characters contained in the text (diagrams 8-11). 6 language are automatically selected by the transmitted page header control bits C12, C13 and C14 (diagram 3, line 25, byte 7) in standardized 7-bit operation (diagram 10 and 11). In addition the capability exist in 8-bit operation, to select nearly all characters independently of the control bits using the I2C bus (diagram 8). Teletext signals R, G, B, Y, BLAN and COR are available at the open-drain outputs. The COR signal makes it possible to reduce the contrast during the mixed mode as well as inside or outside of a teletext box area. The Y signal reproduces only the teletext character plane without color information and does not have a flash function. Diagram 12 shows the active display area. Additional features include:
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User-controllable character-height doubling with top/bottom selection. Status information above or below the main text. Insertion of all control, graphics or alphanumeric characters in the 24 standard rows and in one extra status row is possible via the I2C bus. By doing so the selected position of the character can be made visible by means of a cursor.
Semiconductor Group
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SDA 5248-5
Timing The internal system clock is derived from the 6-MHz clock F6 provided by the data slicer SDA 5231-2. The input F6 is AC coupled internally. Vertical synchronization with the video signal occurs via the VCS input. The noise content of the VCS signal is reduced by integration. If the signal is too noisy or no synchronization can be achieved for other reasons the data acquisition is disabled. The device is able to supervise the quality of the incoming video signal at the VCS input. This is done by means of counting the sync pulses received during 64 s. A good line of a video signal consist of 1 or 2 pulses during 64 s. By means of an integration over the lines of move fields a good and weak signal quality is defined. Under worse signal conditions the data acquisition is stopped. The quality status bit of the VCS signal (VCSOK) is stored in the I2C bus register 11B (see diagram 6). Therefore the microprocessor can be used to supervise the signal quality level. During the normal operation of the SDA 5248-5 (reg. 0, bit d3 = 0) and weak signal quality is detected the IC will automatically switch to the unlocked operation mode. This means PLL and video signal are no longer synchronized. Is the bit d3 set to "1" there is forced synchronization even if the signal quality is weak. The data acquisition will be stopped. But if the signal quality will get weaker it has to be considered that the PLL jitter can be increased. During this operation mode bit d0 in register 11B indicates the quality of the last line received before reading the register. In the normal mode this bit indicates the quality of the VCS signal integrated during some TV fields. One evaluation in the SDA 5248-5 recognizes by good signal (VCSOK = 1) the field frequency of the received VCS signal (50 Hz or 60 Hz) and the result is stored in I2C register 11B (see diagram 6). The TCS/SCS pin can be defined as an input via the I2C bus. 17 s after the start of a line an internal signal is used to sample the input sync signal. (Refer to diagram 13 a and 13 b). Therefore the input signal shall have only low distortions and low noise. The first change from "high" level to "low" level detected by this sampling process initiates the external vertical synchronization of this device (see application circuit 3c). To reduce the hardware expense for the synchronization of the display part i.e. 60-Hz signals (NTSC) the vertical external synchronization of the integrated circuit can also be done via I2C bus through the VCS input (see application circuit 3b). In this case, the bit VCS_to_SCS in I2C register 1, bit d7 (see diagramm 5) must be reset to 1. There is no requirement for an external switch-over circuit including an inversion for the SCS input. At the same time the 6-MHz clock signal F6 and due to this the internal system clock are always synchronized to the input signal. This doesn`t depend on the signal quality of the input signal. Furthermore, the noise components of the sync-signals are reduced by integration. When the TCS/SCS pin is switched as an output it deliners a sync signal (interlaced or noninterlaced) for the TV deflection circuit (see application circuit 3a and diagram 13a). The SAND output delivers a three-level signal which contains the phase-lock signal PL and the color burst blanking signal FBB. The PL signal synchronizes the 6-MHz clock in the SDA 52312. If for some reasons no synchronization is possible, the PL signal component of the sand signal (refer to timing diagram 3) is switched off and the oscillator is running unsynchronized.
Semiconductor Group
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SDA 5248-5
The field recognition output EVEN changes its state once per field. Using this signal it is possible to realize non-interlaced displays. The synchronization of the display can be derived from the acquisition or the display related circuits in the device (e.g. in the after hour operation mode). The display locked synchronization mode can be selected by means of the I2C bus bit VCS_to_SCS set to 1 (register 1, d7 = 1) or the I2C bits "external synchronization" (register 1, d0 = d1 = 1). Otherwise the display synchronization is locked to the acquisition circuit. The line or timing relation of the EVEN output signal can be seen from timing diagram 4. The detector for the first field can be switched off via I2C bus bit register 0,bit d2. The EVEN output will remain in "low" status after the detector is switch off. Memory Interface The following memory types can be connected to the SDA 5248-5 without additional external components: - Dynamic RAMS with 64 K x 4 organization - Dynamic RAMS with 128 K x 4 organization The refresh for the dynamic memory occurs automatically in the range SAND = 0. The circuit configuration for the different memory types are shown in the application circuits 1-2.
Semiconductor Group
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SDA 5248-5
Organization of the Page Memory The external page memory is subdivided into 128 pages of 1 Kbyte each, which are numbered 0 through 127. The different pages 0 - 127 can be selected using the active chapter bits A0 till A7 in the I2C bus register 8 (diagram 6). Bytes within a chapter can be selected via the I2C bus addressing rows (I2C bus register 9) and columns (I2C bus register 10). Please refer to the diagram 6. In the functional block "memory interface" the row and column addresses are automatically converted into the 10 bit wide RAM address. For the display chapter (A2 till A0 in register 4, diagram 6) and acquisition chapter (A2 till A0 in register 2, diagram 5) the addressing is done indirectly via the 8 page memory pointers (I2C bus register 13, diagram 7). Each CHAPTER contains 23 lines with 40 columns each for storing the normal teletext data (diagram 2a). In addition it contains lines 0, 24 and 25. Line 0 is the page header. Line 24 is used to display status information from the control computer (to the user). Line 25 contains information for the control computer and 14 bytes free for optional use. In the ghost-row mode the visible lines are stored in CHAPTER 0-3 and corresponding virtual lines in CHAPTERS 4-7. 8 pages are assigned to the chapters 0-7 by means of the 8 page memory pointers (I2C bus register 13, diagram 7). Diagram 2b shows in which CHAPTER line a virtual line is stored. On switch-on reset, the memory areas 0 till 7 are erased excepted for CHAPTER 0, line 0, column 7, where "alpha-white" (0000 0111) is written. During operation, erasing is possible via I2C bus, but the erasing cycle requires up to 22 ms per page memory. As soon as the control bit C4 for one of the four pages being looked for is transmitted, this page is automatically erased. The actual state of C4 is stored in line 25 (diagram 3). For each 8-bit data word two write or read cycle are necessary. Every cycle requires 250 ns. The timing for the memory interface is given in the characteristics and in the timing diagram 5.
Semiconductor Group
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SDA 5248-5
I2C Bus Organization of the I2C Bus Registers 0010 001 R/W Component address
When the supply voltage is connected, a switch-on-reset is performed. The bus lines SDA and SCL are released. Registers 0-4 and 7-12 are set to 0000 0000, register 5 and 6 to 0000 0011. The page memory pointers in register 13 are set with the values: Page memory 0: Page memory 1: Page memory 2: Page memory 3: Page memory 4: Page memory 5: Page memory 6: Page memory 7: 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111
The circuit functions as slave-transmitter and slave-receiver. Registers R0 to R10, R12, R13 can be written only, register R11 can be written and read (diagram 5 and 6). Note: All reserved bits have to be written with "0".
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SDA 5248-5
Write S
Start
0010
0010
Write
A
Acknowledge
0000
XXXX
A
XXXX
XXXX
AP
Stop
Chip Address Byte
Register Address
Data Word 1
Read S 0010 0010
Write
A
0000
1011
A
S
0010
0011
Read
A
Chip Address Byte XXXX XXXX A
Register A Address 11 A
Chip Address Byte XXXX XXXX P
Data Word 1
Data Words nn
Last Data Word
In several registers, an auto-increment of the register or column address occurs after each byte is written. For example, when register 1 is addressed, the data in register 1, register 2 and the column selected by register 2 in register 3 are written, and an auto-increment of the column addresses 0-6 takes place in R3, i.e. 9 data bytes can follow directly after the register address 1. The bits are numbered in reverse order of the I2C bus data stream.
Semiconductor Group
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SDA 5248-5
Register 0 Bit d7-d6 d5 d6 d3
Register Address 0000 0000
"Pin Function Switch" Comment reserved
Function 0 = S0-pin = low 1 = S0-pin = high 0 = S1-pin = low 1 = S1-pin = high 0 = normal operation 1 = forced sync (free run mode blocked) 0 = EVEN-pin active 1 = EVEN-pin = 0V
no automatic self sync by inferior VCS signal
d2 d1 d0
not used 0 = register 11 A is selected 1 = register 11 B is selected
After a write to register 20 the register address is increased to 1.
Semiconductor Group
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SDA 5248-5
Register 1 Bit d7 d6 d5 d4 d3 d2 d1/d0 d1/d0 d1/d0 d1/d0
Register Address 0000 0001
"Setting the Operational Mode" Comment for 60-Hz display mode parity check of TTX data no parity check reception of lines 25 to 30 DEW = data entry window for line 2-22
TCS/SCS
Function 0 = normal operation 1 = VCS T0 SCS 0 = acquisition of 7 bit and parity bit 1 = acquisition of 8 bit data words 0 = acquisition ON 1 = acquisition OFF 1 = enable GHOST ROWS 0 = DEW 2-22, 1 = full channel operation 1 = TCS ON 00 = 312/313 lines 01 = 312/313 lines 10 = 312/313 lines - MIX - mode - TEXT - mode - TERMINAL - mode
pin is sync output is inhibit in flash messages and subtitles
with interlace without interlace without interlace
TCS/SCS
11 = external synchronization
pin is an input.
After a write to register 1 the register address is auto-incremented to 2.
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SDA 5248-5
Register 2 Bit d7 d6 d5/d4
Register Address 0000 0010
"Page Memory Selection" Comment Not used BANK selection Register 3 selection, ACQCCT0, the acquired page is stored under the page memory address in register 13 page memory pointer 0 or 4. Register 3 selection, ACQCCT1, the acquired page is stored under the page memory address in register 13 page memory pointer 1 or 5. Register 3 selection, ACQCCT2, the acquired page is stored under the page memory address in register 13 page memory pointer 2 or 6. Register 3 selection, ACQCCT3, the acquired page is stored under the page memory address in register 13 page memory pointer 3 or 7. Test bit. With address auto-increment
Function 0 = page memory pointer 0-3 1 = page memory pointer 4-7 00 = page acquisition control ACQCCT0 page memory pointer 0 or 4
d5/d4
01 = page acquisition control ACQCCT1 page memory pointer 1 or 5
d5/d4
10 = page acquisition control ACQCCT2 page memory pointer 2 or 6
d5/d4
11 = page acquisition control ACQCCT3 page memory pointer 3 or 7
d3 d2-d0
1 = TB 0 = normal operation addressing of column 0-6 in register 3
After a write in register 2 the register address is increased to 3.
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SDA 5248-5
Register 3
Register Address 0000 0011
"Page Request Data"
This register contains 7 columns. The column address last written to register 2 is accessed. After every data word the column address in register 2 is auto-incremented. Column Address 000 to 110 Bit d5-d7 are not evaluated
Column Address
Bit d4 1 = do care
Bit d3
Bit d2
Bit d1/d0
000 001 010 011 100 101 110
magazine number tens position units position tens position units position tens position units position
HOLD
(*)
magazine number page number tens position page number units
0
0 hour units
hour tens
0
minute tens minute tens
(*) HOLD = 0
Page contents are not updated During an uninterrupted access to register 3 the HOLD function is automatically performed
Each page data acquisition controller ACQCCT0-3 contain one register 3 (diagram 5). By searching the same page in several registers 3, the page data acquisition with the lowest number has the priority. No auto-increment to register address 4. Register 4 Register Address 0000 0100 "Display Chapter"
Register address must be transmitted (no auto-increment from register 3). Bits 3-7 are not evaluated. Bits 0-2 number of the page memory 0 to 7 in register 13. The page memory refer to the address of the page to be shown.
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SDA 5248-5
After a write to register 4 the register address is auto-incremented to 5. Register 5 Bit d7 Register Address 0000 0101 "Display Control Normal Inside and Outside Box" Comment has priority over "picture outside" has priority over "picture inside"
Function 0 = only for foreground colors outside 1 = foreground and background colors outside 0 = only foreground colors inside 1 = foreground and background colors inside 0 = normal contrast 1 = contrast reduction outside 1 = contrast reduction inside 1 = text outside 1 = text inside 1 = picture outside 1 = picture inside
d6
d5 d4 d3 d2 d1 d0
Inside: Outside:
inside a teletext box area outside a teletext box
After a write to register 5 the register address is auto-increment to 6 Register 6 Register Address 0000 0110 "Display Control News Flash Subtitle"
Function analogous to register 5, valid only for flash messages and subtitles controlled by transmitted control bit C5 or C6. Functions control as in register 5. After a write to register 6 the register address is auto-incremented to 7.
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SDA 5248-5
Register 7 Bit d7 d6
Register Address 0000 0111
"Display Mode" Comment
Function 1 = status information in row 0 0 = status information in row 24 1 = cursor "ON" for position addressed in reg. 9 and 10 0 = cursor "OFF" 0 = reveal function activated 01 = double character height, only lines 0-11 visible 11 = double character height only lines 12-23 visible X0 = normal image 1 = box on attribute enable in line 24 1 = box on attribute enable in line 1-23 1 = box on attribute enable in line 0
cursor blinking is possible by repeated switching ON and OFF after conceal display controller character
d5 d4/d3
d2 d1 d0
a0 in d1 inhibits the display of flash messages and subtitle
No auto-increment to register 8 Register 8 Register Address 0000 1000 "Active Chapter"
Register address must be sent (no auto-increment from register 7) The bits 4-7 have no function. Bit 3-1, erasing memory contents of the addressed page. The bit is not stored. Within one frame period, the blanking code 0010 0000 is written to all memory positions of line 0, column 0 to line 25, column 23. Bit 0-2, the page memory addressed 0...127 for I2C bus access. All pages can Bit 4-7 be addressed directly. After a write to register 8 the register address is auto-incremented to 9.
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SDA 5248-5
Register 9 Bit 5-7 Bit 0-4
Register Address 0000 1001
"Active Row"
without function selection of rows 0-25 in page memory.
Auto-increment of row address. Row 23 is followed by row 0. Rows 24 a. 25 can only be selected directly. After a write to register 9 the register address is auto-incremented to 10. Register 10 Bit d6 and d7 Bit d0-d5 Register Address 0000 1010 without function selection of columns 0-39 in page memory "Active Column"
An auto-increment of the column address follows. Column 39 followed by column 0 and an auto-increment of the line address in register 9. After a write to register 10 the register address is auto-incremented to 11. Register 11A Register Address 0000 1011 and Register 0, d0 = 0 "Active Data" Data Bit Alphanumeric and control characters d7 Bit 8 d6 Bit 7 d5 Bit 6 d4 Bit 5 d3 Bit 4 d2 Bit 3 d1 Bit 2 d0 Bit 1
After writing a data byte, the column address is auto-incremented for the next data byte. After reading a data byte the position of the next byte to be read is automatically selected, if the last write command selected automatical the register 11 or if the last write command created an auto-increment from register 10 to register 11.
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SDA 5248-5
Register 11B
Register Address 0000 1011 and Register 0, d0 = 1 "Status Register" Comment valid only for "VCS is OK." for d0 = 0 no used (d7 always 0) register 0, d3=0
Bit d7
Function 0 = 50-Hz VCS signal available 1 = 60-Hz VCS signal available 0 0 = VCS signal is interferred 1 = VCS is ok 0 = last VCS line was interferred 1 = last VCS line was interferred
d6-d1 d0
register 0, d3 = 1
Write access to register 11B is impossible, if write access with the address 11B is attempted as a direct write access to the page memory by means of register 11A. No auto-increment to register address 12. Register 12 Register Address 0000 1100 "Address for Page Memory Pointers"
Bit d3 - d7 Bit d0 - d2
without function. page address selection in register 13
After a write to register 12 the register address is auto-incremented to register address 13.
Register 13
Register address 0000 1101
"Page Memory Pointer"
This register contains 8 columns. The page address last written to register 12 is accessed. After writing of an address into register 13 the content of register 12 is automatically incremented. Therefore the next data byte received is automatically written into the next page memory pointer. Bit d7 Bit d0 - d6 without function address bit for page address
All 8 page memory pointers have to contain different addresses otherwise different acquired pages are written into the same area of the memory. After power-on reset the address pointers contain the page memory addresses 0-7.
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SDA 5248-5
Absolute Maximum Ratings T A = 25 C (all voltages are referred to V SS) Parameter Supply voltage Voltages at: VCS, SAND, SDA, SCL, EVEN D0 to D3, A0 to A8 OE, WE, CAS, RAS, S0, S1 TTC, F6
TSC/SCS,
Symbol min. V DD - 0.3
Limit Values typ. max. 6
Unit V
V IN V IN V IN VA TA T stg P tot R th
- 0.3 - 0.3 - 0.3 - 0.3 - 20 - 20 39
V DD 11 8.5 6.5 70 125 1.3
V V V V C C W K/W
TTD
R, G, B, BLAN, Y,COR Ambient temperature Storage temperature Power dissipation Thermal resistance Operating Range Supply voltage Temperature
V DD TA
4.5 0
5.5 70
V C
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SDA 5248-5
Characteristics T A = 25C (all voltages referenced to V SS) Parameter Supply voltage Supply current Symbol V DD V DDA I DD I DDA 4.5 4.5 80 2 Limit Values min. typ. 5 5 160 4 max. 5.5 5.5 220 10 V V mA mA without load F6 = 6 MHz Unit Test Condition
Inputs TTC and F6 Input voltage*) Input signal*) Input leakage current Input capacitance Input frequency Input frequency Rise and fall times Input TTD Input signal**) Input leakage current Input capacitance Rise and fall times Ext. coupling capacitor ***)
*) **) ***)
V IP V IPP II CI f TTC f F6 t r, t f
- 0.3 1
10 7 20 7
V V
A
min. and max. values V I = 0 - 10 V
pF MHz MHz ns
4 4 10
6.9375 8 6.0 8 80
V IPP II CI t r, t f C ext
2
7 20 7
Vpp
A
V I = 5.5 V
pF ns nF
10
80 50
timing diagram 1 test circuit 2, timing diagram 2 test circuit2
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SDA 5248-5
Characteristics (cont'd) Parameter Symbol Limit Values min. Input VCS L - input voltage H - input voltage*) Input leakage current Input capacitance Rise and fall times Input SCL, Input/Output SDA L - input voltage H - input voltage Input leakage current Input capacitance Input frequency Rise and fall times Max. capacity of bus Fall time (acknowledge) SDA acknowledge
*)
Unit
Test Condition
typ.
max.
V IL V IH II CI t r, t f
0
0.8 V DD 10 7 500
V V
A
V I = 5.5 V
pF ns
V IL V IH II CI f SCL t r, t f C max tf V AL
0 3
1.5 V DD 10 7 100 2 400 0.2
V V
A
V I = 5.5 V
pF kHz
s
pF
s
from 3 to 1 V I AL = 3 mA
0
0.5
V
test circuit 2
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SDA 5248-5
Characteristics (cont'd) Parameter Symbol Limit Values min. Input/Output TCS/SCS Input signal SCS L - input voltage H - input voltage Input capacitance Input leakage current Rise and fall times Output Signal TSC L - output voltage H - output voltage Load capacitance Rise and fall times V QL V QH CL t r, t f 0 2.4 0.4 V DD 5.5 50 100 V V V pF ns between 0.6 and 2.2 V I QL = 1.6 mA - I QH = 0.2 mA I QH = 0.1 mA
(TSC =
Unit
Test Condition
typ.
max.
high impedance) 0 3.5 1.5 8 7 10 500 V V pF A ns VI= 8 V
V IL V IH CI II t r, t f
RAM Data Interface D0 - D3 (Tristate input/output) L - input voltage H - input voltage Input leakage current Input capacitance L - output voltage H - output voltage Rise and fall times Load capacitance V IL V IH II CI V QL V QH t r, t f CL 0 2.4 0 2 0.8 V DD 10 7 0.4 V DD 20 50 V V A pF V V ns pF I QL = 1.6 mA - I QH = 0.2 mA between 0.6 and 2.2 V, output active V I = 5.5 V
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47
SDA 5248-5
Characteristics (cont'd) Parameter Symbol Limit Values min. Output EVEN L - output voltage H - output voltage Rise and fall times Load capacitance Output SAND L - output voltage Intermediate level*) H - output voltage Rise time Fall time Load capacitance V QL V QM V QH t r1 t r2 tf CL 0 1.1 4.0 0.25 2.9 V DD 400 200 50 30 V V V ns ns ns pF I QL = 0.6 mA I QM = 30 A V QL V QH t r, t f CL 0 2.4 0.4 V DD 100 50 V V ns pF I QL = 1.6 mA - I QH = 0.2 mA between 0.6 and 2.2 V typ. max. Unit Test Condition
- I QH = 30 A
between 0.4 and 1.1 V between 2.9 and 4 V between 4 and 0.4 V
RAM Address Outputs OE, WE, A0 - A8, RAS, CAS L - output voltage H - output voltage Rise and fall times Load capacitance Switch Outputs S0, S1 L - output voltage H - output voltage Rise and fall times Load capacitance
*) timing diagram 3
V QL V QH t r, t f CL
0 2.4
0.4 V DD 20 50
V V ns pF
I QL = 1.6 mA - I QH = 0.2 mA between 0.6 and 2.2 V
V QL V QH t r, t f CL
0 2.4
0.4 V DD 50 120
V V ns pF
I QL = 1.6 mA - I QH = 0.2 mA between 0.6 and 2.2 V
Semiconductor Group
48
SDA 5248-5
Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Condition
Outputs R, G, B, BLAN, Y, COR (open drain output) L - output voltage V QL H - output voltage Fall time (Test circuit 1) Fall delay (Test circuit 1) Output leakage Load capacitance V QH t t
f
0 0 4.9
0.4 1 5 20
V V V ns ns
A
I QL = 2 mA I QL = 5 mA R L = 1 k an 5 V R L = 1 k by 5 V V PIN = 4.5 1.5 V with R L =1 k by 5 V V Q= 5 V
d
20 IQ CL 20 25
pF
Timing for Memory Interface Cycle time (page mode)**) Delay address to OE *) Pulse duration OE *) Row address hold hold time**) Column address hold time**) Row address set-up time**) Column address set-up time**) Data set-up time*) Data hold time*) Pulse duration RAS (page mode)**) Pulse duration CAS **) Set-up time RAS
*) **) **)
t RC, t WC t OE t OEL t RAH t CAH t ASR t ASC t CAC t OFF t RASP t CASL t RP
450
500
500 10
ns ns ns ns ns ns ns
400 25 60 5 5 60 0 280 80 100
ns ns ns ns ns
timing diagram 5b timing diagram 5a, timing diagram 5b
Semiconductor Group
49
SDA 5248-5
Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Condition
Timing for Memory Interface (cont'd) (test circuit 5a, timing diagram 5b) Set-up time CAS**) Set-up time CAS**) Delay WE*) Pulse duratio WE Data hold time*) to tristate*) PLL Filter Currents Load current Load current Load current Load current
*) **) *)
t RP t CP t WE t WEL t DS t DH t OHZ
100 55 10 300 10 60 40
ns ns ns ns ns ns ns
Data set-up time*)
I CH I CH I DCH I DCH
20 20 - 20 - 20
80 80 - 80 - 80
200 200 - 200 - 200
A A A A
V OL = 1.9 V V OH = 2.5 V V OL = 1.9 V V OL = 2.5 V
timing diagram 5a timing diagram 5a, timing diagram 5b
Components Used for the PLL Loop Filter (see test circuit 3) CF1 1.6 nF, CF2 100 pF R F 1.8 k
Semiconductor Group
50
SDA 5248-5
Test Circuit 1
Test Circuit 2
Test Circuit 3
. Semiconductor Group 51
SDA 5248-5
Timing Diagram 1 Input Signals TTC and F6
Timing Diagram 2 Input Signals TTC and TTD
Semiconductor Group
52
SDA 5248-5
Timing Diagram 3 TCS and SANDCASTLE-Output
Timing Diagram 4a
Semiconductor Group
53
SDA 5248-5
Timing Diagram 4b
Semiconductor Group
54
SDA 5248-5
Timing Diagram 5a Data Transfer with External Memory Dynamic Memory 64 K x 4 or 128 K x 4 Memory Write (Page Mode Write Cycle)
Semiconductor Group
55
SDA 5248-5
Timing Diagram 5b Data Transfer with External Page Memory Dynamic Memory 64 K x 4 or 256 K x 4 Memory Read (Page Mode Read Cycle)
Semiconductor Group
56
SDA 5248-5
Application Circuit 1 SDA 5248-5 Interfacing to 64 K x 4 Dynamic RAM for 32 Pages
Semiconductor Group
57
SDA 5248-5
Application Circuit 2 SDA 5248-5 Interfacing to 256 K x 4 RAM for 128 Pages
Semiconductor Group
58
SDA 5248-5
Application Circuit 3a Teletext System Timing with CVBS Synchronization
Semiconductor Group
59
SDA 5248-5
Application Circuit 3b Teletext Clock Control in 60-Hz Display Mode
Semiconductor Group
60
SDA 5248-5
Application Circuit 3c Teletext Clock Control wit External Synchronization
Semiconductor Group
61
SDA 5248-5
Application Circuit 4 Semiconductor Group 62
SDA 5248-5
Application Circuit 5 Semiconductor Group 63
SDA 5248-5
Diagram 1 Teletext Input Signal (Line 2 to 22 and 315 to 335)
Semiconductor Group
64
SDA 5248-5
Diagram 2 Page Memory Organization
* Automatic erasable lines with RESET, CLEAR MEMORY or control bit C4
Semiconductor Group
65
SDA 5248-5
Diagram 3 Virtual Page (Ghost Rows) * ** Automatic erasable lines with RESET, CLEAR MEMORY or control bit C4 In 7-bit mode (register 1) the marking bytes are checked DD parity and MSB is set to. Defective bytes are not tacked over in the page memory. 66
Semiconductor Group
SDA 5248-5
Diagram 4 Page Memory Organization Line 25, Byte 0....9 Byte D7 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 0 0 Data Bits D6 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 PBLF D4 HA HA HA HA HA HA HA HA
FOUND
D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0
D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0
D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0
D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0
0
Information Bits HA
FOUND
PBLF
= = =
High, Hamming error found in corresponding column Low, when a header has been found High, page search in progress
Page Number MAG PU PT MU MT HU HT = = = = = = = Magazine number 0 to 7 (000....111) Page number units (0...9) Page number tens (0...9) Minutes units Minutes ten usable as additional page sub Hour units code Hour ten
Control Bits C4 = erase page C5 = news flash C6 = subtitle C7 = C8 = C9 = C10 = inhibit display C11 = serial magazine sequence C12, C13, C14 character set selection Semiconductor Group 67 suppress header update indicator interrupted sequence
SDA 5248-5
d7 Register 0 *
d6 *
d5 S1
d4 S0
d3 NO FREE RUN DEW FULL TB
d2 EVEN OFF TCS
d1 *
d0 SEL 11B
Bit Mode 0
Register 1
VSC TO SCS
7+P
ACQ
GHOST ROW ENABLE ACQ CCT A0
Sync-Mode 1
Sync-Mode 0
Mode 1
Register 2
*
BANK SELECT A2
ACQ CCT A1
START ROW SR2
START ROW SR1
START ROW SR0
Page Request Address
RAM ACCESS REGISTER d4 DO CARE DO CARE DO CARE 4 X Register 3 DO CARE DO CARE DO CARE DO CARE d3 HOLD d2 MAG2 d1 MAG1 d0 MAG0 Bit ROW 0 (MAGAZINE)
PT3
PT2
PT1
PT0
ROW 1 (PAGE TENS)
PU3
PU2
PU1
PU0
ROW 2 (PAGE UNITS)
Page Request Data
*
*
HT1
HT0
ROW 3 (HOURS) *not defined (Bits have to be written with "0")
HU3
HU2
HU1
HU0
ROW 4 (HOURS)
*
MT2
MT1
MT0
ROW 5 (MIN. TENS)
MU3
MU2
MU1
MU0
ROW 5 (MIN. UNITS)
ACQ CCT0 ACQ CCT1 ACQ CCT2 ACQ CCT3
Diagram 5 Register Configuration Semiconductor Group 68
SDA 5248-5
d7 Register 4 *
d6 *
d5 *
d4 *
d3 *
d2 A2
d1 A1
d0 A0
Bit DISPLAY CHAPTER
Register 5
BACKGROUND OUT
BACKGROUND IN
CONTRAST CONTRAST TEXT OUT REDUCREDUCTION TION OUT IN
TEXT IN
PICTURE OUT
PICTURE IN
DISPLAY CONTROL NORMAL INSIDE AND OUTSIDE BOX
Register 6
BACKGROUND OUT
BACKGROUND IN
CONTRAST CONTRAST TEXT OUT REDUCREDUCTION TION OUT IN
TEXT IN
PICTURE OUT
PICTURE IN
DISPLAY CONTROL NEWS FLASH OR SUBTITLE DISPLAY MODE
Register 7
STATUS ROW BTM TOP
CURSOR ON
CONCEAL TO BOTTOM REVEAL
SINGLE DOUBLE HEIGHT
BOX ON 24
BOX ON 1 - 23
BOX ON 0
RAM ACCESS REGISTER d7 Register 8 A6 d6 A5 d5 A4 d4 A3 d3 CLEAR MODE d2 A2 d1 A1 d0 A0 Bit ACTIVE CHAPTER
Register 9
*
*
*
R4
R3
R2
R1
R0
ACTIVE ROW ACTIVE COLUMN ACTIVE DATA STATUS
Register 10 Register 11A Register 11B
*
*
C5
C4
C3
C2
C1
C0
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
60 Hz
0
0
0
0
0
0
VCSOK/ LLNOR
* not defined (Register have to be written with "0")
Diagram 6 Register Configuration Semiconductor Group 69
SDA 5248-5
Register 12
*
*
*
*
*
PA2
PA1
PA0
Address for Page Memory Pointers
8 x Register 13
* * * * * * * *
A6 A6 A6 A6 A6 A6 A6 A6
A5 A5 A5 A5 A5 A5 A5 A5
A4 A4 A4 A4 A4 A4 A4 A4
A3 A3 A3 A3 A3 A3 A3 A3
A2 A2 A2 A2 A2 A2 A2 A2
A1 A1 A1 A1 A1 A1 A1 A1
A0 A0 A0 A0 A0 A0 A0 A0
Page Memory Pointer 0 Page Memory Pointer 1 Page Memory Pointer 2 Page Memory Pointer 3 Page Memory Pointer 4 Page Memory Pointer 5 Page Memory Pointer 6 Page Memory Pointer 7
* not defined (Register have to be written with "0")
Diagram 7 Register Configuration Semiconductor Group 70
SDA 5248-5
Diagram 8.1 Character Set Selection Display of the Complete Character Set SDA 5248-5C1
(1) Reset before the start of each row (2) Is implemented for the control character and not just the following characters (3) These control characters have to be transmitted twice in succession implementation begins between control characters (4) Not implemented
Comment: The random access to , and can be done only when the language selection bits C12, C13, C14 are adjusted to the German language.
Semiconductor Group
71
SDA 5248-5
Diagram 9.1 Graphic Characters SDA 5248-5C1 (West European) Graphics mode is activated by control character (0001 0XXX). Semiconductor Group 72
SDA 5248-5
Diagram 10a SDA 5248-5C1 (West European) 10.1 National Character Set Selection Using the Transmitted Control Bits Bit 8 transmitted parity bit is reset to 0. The national characters in diagram 10 are implemented in the corresponding positions in diagram 9.2.
Transmitter Control bits C12 C13 C14
SDA 5248-5C1
English German Swedish Italian
French Spanish Dynamic Reserve Character Redefinition
0 0 0
0 0 1
0 1 0
0 1 1 Italian
1 0 0 French
1 0 1 Spanish
1 1 0 English
1 1 1 English
Siemens English German Swedish
Semiconductor Group
73
SDA 5248-5
Diagram 10.2 Basic Character Set SDA 5248-5C1 (West European) Basic character set (code: high nibble/low nibble for bit 8 = 0) NC = National Character (diagram 11)
Semiconductor Group
74
SDA 5248-5
Diagram 11.1a National Characters (NC) SDA 5248-5C1 (West European) Semiconductor Group 75
SDA 5248-5
Diagram 11.1b National Characters (NC) SDA 5248-5C1 (West European) Fixed special characters
Semiconductor Group
76
SDA 5248-5
Diagram 8.2 Character Set Selection (East European) Display of the Complete Character Set SDA 5248-5C2
(1) Reset before the start of each row (2) Is implemented for the control character and not just the following characters (3) These control characters have to be transmitted twice in succession implementation begins between control characters (4) Not implemented
Comment: The random access to , and can be done only when the language selection bits C12, C13, C14 are adjusted to the German language.
Semiconductor Group
77
SDA 5248-5
Diagram 9.2 Graphic Characters (East European) SDA 5248-5C2 Graphics mode is activated by control character (0001 )XXX). Semiconductor Group 78
SDA 5248-5
Diagram 10.b SDA 5248-5C2 (East European) 10.1 National Character Set Selection Using the Transmitted Control Bits Bit 8 transmitted parity bit is reset to 0. The national characters in diagram 11are implemented in the corresponding positions in diagram 10.2.
Transmitter Control bits C12 C13 C14
SDA 5248-5C2
English German Swedish Italian
French Spanish Dynamic Reserve Character Redefinition
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0 CzechSlovak
1 1 1 Romania
Siemens Polish
German Scandinavian
German German Serbocroat
Semiconductor Group
79
SDA 5248-5
Diagram 10.2 Basic Character Set SDA 5248-5C2 (East European) Basic character set (code: high nibble/low nibble for bit 8 = 0) NC = National Character (diagram 11)
Semiconductor Group
80
SDA 5248-5
Diagram 11.2a National Characters SDA 5248-5C1 (NC) SDA 5248-5C2 (East European) Semiconductor Group 81
SDA 5248-5
Diagram 11.2b National Characters (NC) SDA 5248-5C2 (East European) Fixed special characters
Semiconductor Group
82
SDA 5248-5
Diagram 12
Semiconductor Group
83
SDA 5248-5
Composite sync TCS contains line sync equalizing pulses and main pulses. D, e, f are the vertical sync signals with line numbers. Diagram 13a Raster Change Frequency 50 Hz Semiconductor Group 84
SDA 5248-5
Diagram 13b Raster Change Frequency 60 Hz Semiconductor Group 85
SDA 5248-5
Layout / Plug-In Location Plan
Semiconductor Group
86
SDA 5248-5
Plug-In Location Plan
Semiconductor Group
87
SDA 5248-5
Diagram 14a Display of the Complete Character Set SDA 5248-5TR
(1) Reset before the start of each row (2) Is implemented for the control character and not just the following characters (3) These control characters have to be transmitted twice in succession implementation begins between control characters (4) Not implemented
Comment: The random access to , and can be done only when the language selection bits C12, C13, C14 are adjusted to the German language.
Semiconductor Group
88
SDA 5248-5
Diagram 14b Graphic Characters turkish Character Set SDA 5248-5 Graphics mode is activated by control character (0001 0XXX) Semiconductor Group 89
SDA 5248-5
9.1 National Character Set Selection Using the Transmitted Control Bits Transmitted parity bit is reset to 0. The national characters in diagram 10 are implemented in the corresponding positions in diagram 9.2.
Transmitter Control bits C12 C13 C14
English German Swedish Italian
French Spanish Dynamic Reserve Character Redefinition
0 0 0
0 0 1
0 1 0
0 1 1 Italian
1 0 0 French
1 0 1 Spanish
1 1 0 Turkish
1 1 1 English
Siemens English German English SDA 5343 TR
Semiconductor Group
90
SDA 5248-5
Diagram 9.2 Basic Character Set Basic character set (code: high nibble/low nibble for bit 8 = 0) NC = National Character (diagram 10)
Semiconductor Group
91
SDA 5248-5
Diagram 15a National Characters (NC) SDA 5248-5TR
Semiconductor Group
92
SDA 5248-5
Diagram 15b National Characters (NC) SDA 5248-5TR
Semiconductor Group
93

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